Days:
Friday
& Sunday
Time: 6:00 PM - 8:30 PM
Duration: 10 Weeks
Mode: On Campus
This course provides a comprehensive understanding of the front-end and back-end flow of digital VLSI design, from Register-Transfer Level (RTL) coding to physical implementation (Place & Route). It is intended for students, researchers, and professionals aiming to gain practical and theoretical knowledge in the entire ASIC/FPGA design cycle.
By the end of this course, learners will be able to:
Write efficient RTL code using Verilog/SystemVerilog/VHDL.
Perform functional verification using testbenches and simulation tools.
Apply synthesis techniques and understand timing constraints (SDC).
Execute static timing analysis and power analysis.
Understand the complete PnR flow: floorplanning → placement → CTS → routing → optimization.
Gain exposure to industry-standard EDA tools used in VLSI design.
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